Static Noise Margin Analysis of Low Power SRAM Cell for High Speed Application

Low power design is the industry buzzword these days in present chip design technologies. CMOS technology continues to drive the reduction in switching delay and power while improving area density. However, the transistor miniaturization also introduces many new challenges in Very Large Integrated (VLSI) circuit design, such as sensitivity to process variations, increasing transistor leakage and reducing Static Noise Margin. This paper is focused on the different types of analysis applied on noise, voltage, read and write margin of Static Random Access Memory (SRAM) cell for high-speed application and to get an appropriate Static Noise Margin (SNM). The analysis is performed on Cadence virtuoso tool, gpdk 180nm technology. Keywords— Static Noise Margin, SRAM, VLSI, CMOS